Embodiments of the inventive concepts disclosed herein relate generally to power interruptions within a processor. More particularly, embodiments of the inventive concepts disclosed herein relate to a system and method for monitoring a power state within a processor and taking corrective action should a power event occur.
Short duration power interruptions to a processor power supply may have traditionally required the processor to go through a warm start reset. A traditional warm start may send a signal to the system software that the software should begin certain time saving optimizations to facilitate bringing the system back into normal operation once the power interruption is complete. A warm start may attempt a quick restart of the system capabilities to ensure nearly continuous supply of information to a system.
Similarly, a traditional cold startup procedure may depower a system for a longer period than a warm start in order to attempt to regain full processor operation. This lengthy cold startup may reflect an attempt at a system shutdown followed by a restart to attempt to regain full processing capacity.
In a processing system supporting a mission critical display, cold starts may be reason to discontinue authorization and use of a processing system as a lack of a critical display for any substantial length of time may be unacceptable to an operator. In addition, warm starts causing a delay in display availability for even a short duration may be cause for discontinuing use of the processor. As mission critical display requirements may increase in number and complexity, and a proportional increase in processor support capability, operator reliance on continuous operation of these mission critical display systems may also increase.
Use of multi-core processors (e.g., Freescale T2080) in mission critical avionics with embedded hypervisors may allow simultaneous hosting of multiple operating system images. The number of images and their respective size may create a delay in meeting a timing requirement for recovering from a power interruption event. Traditional warm start architecture may meet the timing requirements for the short term but does not scale well and will most likely be unable to meet those requirements in the long term.
Therefore, a need remains for a power monitoring system to ensure mission critical display processors remain adequately operational in the event of a power interruption. Where processor power supplies may be less than perfect, such a power monitoring system and method may offer the operator a continuous operational mission critical display system to enhance operator awareness and increase the operator's ability to successfully accomplish an assigned mission.